Many modern data processing systems utilize dynamic random access memory (DRAM) integrated circuits for main solid-state data storage, due to the high density and low cost storage provided by this technology. These advantages of DRAM storage result from the use of single capacitor and a single access transistor as the DRAM storage cell. In contrast, conventional static random access memory (SRAM) storage cells are constructed as cross-coupled inverters with access transistors, generally requiring either six transistors, or alternatively four transistors and two resistors. As such, the silicon area required to fabricate a given number of DRAM cells, and thus the cost per bit of DRAM memory, is much smaller than that required for conventional SRAM integrated circuits. Accordingly, modern data processing systems and functions that require large memory capacity, for example millions of bytes, often use DRAM integrated circuits to implement such storage.
This construction of the basic DRAM storage cell requires that the contents of DRAM memory be periodically refreshed, to account for natural charge loss from the storage capacitors. Such refresh is conventionally effected by operating the DRAMso that sense amplifiers and restore circuitry within the DRAM sense the data state of a number of DRAM cells and restore the sensed state back into the cells. Conventional DRAMs have a refresh specification time period, on the order of milliseconds, within which each storage cell must be refreshed in order to guarantee retention of the stored contents.
As is well known in the art, refresh may be accomplished for a selected row of DRAM cells by the presentation of the corresponding row address in combination with a row address strobe (RAS) clock. Refresh according to this operation thus requires that the user store or otherwise monitor the addresses presented to the memory to ensure that all rows in the DRAMs are so accessed within the refresh specification period. In addition, many modern DRAMs operate according to a special cycle, in which a row of DRAM cells are selected according to the contents of an on-chip refresh address counter, and are refreshed in the special cycle; an example of such a special cycle is where the column address strobe (CAS.sub.-) is initiated prior to the row address strobe (RAS.sub.-), commonly referred to as CAS-before-RAS refresh. When using CAS-before-RAS cycles to refresh the DRAM, the user need not store or monitor the refresh addresses presented, but need only ensure that the proper number of such cycles are initiated within the refresh specification period.
In the system context, therefore, access to the DRAM memory must be periodically suspended in order to perform the necessary refresh. Conventional systems generally include timer circuitry which monitor the time since the most recent refresh operation, and initiate a refresh operation when necessary. Refresh may be accomplished in a distributed fashion, where a single refresh cycle is periodically performed, or in a burst fashion where many or all refresh cycles are performed less frequently than in distributed refresh. In either case, the DRAM memory is unavailable for a certain fraction of time, necessarily slowing system operation as a result. The relative efficiencies of distributed and burst refresh will depend upon the particular system context, and the urgency at which access to DRAM is required in normal system operation.
Many conventional data processing systems are constructed in such a manner that the DRAM memory and several data processing circuits are interconnected by way of a bus. In systems of this type, it is necessary that all unrelated bus traffic cease during such time as a refresh is being performed. The time required for DRAM refresh in these systems thus degrades system performance not only from a memory availability standpoint, but also because of the time that the bus is unavailable during DRAM refresh, precluding other non-memory access bus traffic during that time.
A particularly sensitive type of data processing system to refresh operations are those used in communications, such as local-area-network (LAN) controllers. In these systems, several data processing circuits, such as microprocessors, are connected to the bus and effect high speed data communication by transferring data among one another via the bus, for example by way of direct memory access (DMA). The bus traffic in such systems will generally be quite heavy; in addition, many messages may be quite long, occupying the bus for relatively long contiguous blocks of time.
As such, refresh is initiated in many bus architecture data processing systems by interrupting bus cycles that are in progress at such time as refresh is necessary, allowing the refresh operation to control the bus. Interruption of a bus cycle requires that the interrupted operation be restarted at such time as it can be granted access to the bus, thus requiring the operations of temporarily storing and later retrieving parameters necessary to restart the interrupted operation. Accordingly, DRAM refresh can cause significant system performance degradation, especially as the number of bus masters on the bus, and the bus traffic, each increase.
Another conventional method of effecting refresh in bus architecture systems is by way of "cycle stealing". According to this technique, the operation of the host microprocessor is monitored to determine when an operation is being performed that does not require the bus, such as an operation internal to the microprocessor. When such an operation is detected, a refresh is initiated and performed in parallel with the internal microprocessor operation, thus utilizing the memory and bus during those operations for which neither is being accessed.
In recent years, however, significant advances have been made to reduce the cycle time required for an internal microprocessor operation. Very short cycle times preclude the cycle stealing approach to refresh, since the decoding time required to determine that an internal operation is being performed may not leave sufficient time in the cycle to accomplish refresh, forcing a wait state at the end of refresh. Accordingly, the effectiveness of the cycle stealing technique is reduced in high speed microprocessor systems.
In addition, as the number of potential bus masters increases, such as in communication systems, the complexity of the circuitry required for implementing refresh according to the cycle stealing technique also increases, and becomes more cumbersome. The efficiency of this technique is therefore also reduced in complex systems constructed according to bus architectures. The cycle stealing operation becomes even more cumbersome when the number of bus masters necessitates bus splitting, especially where the bus masters are bidirectionally connected to the bus.
It is therefore an object of the present invention to provide DRAM refresh control circuitry, and a method of refreshing DRAM memory, which minimize bus cycle interruption to accomplish refresh.
It is a further object of the present invention to provide such a method and circuitry which have a high priority mode to ensure that refresh specifications are not violated.
It is a further object of the present invention to provide such a method and circuitry which operate in a manner consistent with high speed communication systems.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification in combination with the drawings.